Low drop-out (LDO) voltage regulators are widely used to supply power to integrated circuits due to their ability to operate at a low voltage and their high power efficiency. An LDO voltage regulator is a voltage regulator which is able to regulate an output voltage to a predefined value with a very low difference between an input voltage and the output voltage. Such a voltage regulator may be embedded in an integrated circuit or may be provided externally.
A typical LDO voltage regulator known in the prior art comprises an output stage implemented as common source or common emitter transistor amplifier and an error amplifier arranged in a regulation loop which generates an error signal by comparing the output voltage to a reference voltage and which drives the output stage with the error signal.
An LDO voltage regulator 30 suitable for implementation in a Complementary Metal Oxide Semiconductor (CMOS) device is illustrated in FIG. 1. An input voltage VDD is supplied to a source of an output transistor 14, which is a p-channel metal oxide semiconductor field effect transistor (MOSFET), and the output voltage VOUT is delivered at a drain of the output transistor 14. Coupled between the drain of the output transistor 14 and a node, which may be a ground, are series coupled resistors R1 and R2. The junction of the series coupled resistors R1, R2 is coupled to a non-inverting input of an error amplifier 12. An inverting input of the error amplifier 12 is coupled to a reference voltage VREF, and an output of the error amplifier 12 is coupled to a gate of the output transistor 14. The output voltage VOUT is delivered to a load, which is represented by a load resistive element RL coupled to the drain of the output transistor 14. In order to decouple the voltage regulator 30 from the load, a load capacitive element CL is coupled to the drain of the output transistor 14 in parallel with the load resistive element RL. In order to ensure stability, a series coupled feedback capacitor CF and feedback resistor RF are coupled between the drain and a gate of the output transistor 14. The feedback capacitor CF can require a large silicon area for implementation in an integrated circuit. The load capacitive element CL can require an even larger silicon area, or can necessitate the use of an external discrete component. The use of an external discrete component can be undesirable due to the additional space required and parasitic components introduced by additional interconnections. Furthermore, the presence of the feedback capacitor CF can reduce the speed of operation of the voltage regulator 30, resulting in fast changes in the output voltage VOUT when fast changes occur in the current drawn by a load coupled to the output voltage VOUT, such as can occur when parts of load circuits are switched on and off for power conservation. Fast changes in the output voltage VOUT can be reduced by means of filtering using a suitably large load capacitive element CL, although the load capacitive element CL can also reduce the stability of the voltage regulator 30, which can oscillate if the load capacitive element CL is very large.
An alternative voltage regulator 40 known in the prior art is illustrated in FIG. 2. Its architecture differs from the architecture of the LDO voltage regulator 30 of FIG. 1 in two respects. First, its output stage comprises an n-channel MOSFET output transistor 16 with its drain coupled to the input voltage VDD and the output voltage VOUT delivered at its source. This configuration has improved stability, because the output transistor 16 normally doesn't introduce a dominant pole in the frequency range where the voltage regulator 40 has gain. Second, due to the improved stability, the feedback capacitor CF and feedback resistor RF of the LDO voltage regulator of FIG. 1 are omitted. However, the voltage regulator 40 of FIG. 2 is not an LDO voltage regulator. This is because the error amplifier 12 has to be capable of delivering at its output a voltage exceeding VOUT+VGS, where VGS is the gate-source threshold voltage of the output transistor 16 which is normally in the range 0.6 to 0.7 volts, and therefore the input voltage VDD must also exceed VOUT+VGS.
A further voltage regulator 50 known in the prior art is illustrated in FIG. 3. Its architecture differs from the architecture of the voltage regulator 40 of FIG. 2 by employing a charge pump 18 to convert the input voltage VDD to a higher voltage VH, for example double the output voltage VDD, by charging a storage capacitor CQ2. The higher voltage VH is supplied to the error amplifier 12. This architecture can enable LDO operation. However, the storage capacitor CQ2, and a pump capacitor CQ1 required for the operation of the charge pump 18, can require a large silicon area for implementation in an integrated circuit, and the higher voltage VH may exceed the technological limits of modern sub-micron technologies. Also, this architecture can result in increased power consumption.